Input points: 16 points.
Voltage: AC200 ~ 240V.
Current: 10mA.
Response time: 25ms.
16 points / a common end..
20 point terminal station.
System program memory for storing system program,
Including management procedures, monitoring procedures, as well as the user program to do the compiler to compile the process of interpretation.
Read only memory. Manufacturers use, content can not be changed, power does not disappear HF-SP51BK
PLC selection with the development of PLC technology, more and more types of PLC products,
Function is becoming more and more perfect, and its application is more and more extensive.
Different series of different models of PLC has different performance, applicable occasions also have different emphasis,
Price also has a greater difference. Therefore PLC selection,
Under the premise of meeting the control requirements,
Should consider the best performance to price ratio, a reasonable choice of PLC.
Each scanning process. Focus on the input signal sampling. Focus on the output signal to refresh.
Input refresh process. When the input port is closed,
Program in the implementation phase, the input end of a new state, the new state can not be read.
Only when the program is scanned, the new state is read.
A scan cycle is divided into the input sample, the program execution, the output refresh.
The contents of the component image register are changed with the change of the execution of the program.
The length of the scan cycle is determined by the three.
CPU the speed of executing instructions.
Time of instruction.
Instruction count.
Due to the adoption of centralized sampling.
Centralized output mode.
There exist input / output hysteresis phenomena, i.e., the input / output response delay. Input and output (DC/ differential).
Input points: 12 points (DC5V/DC24V/ differential universal).
Pulse input speed: the highest pulse/s 8M (2MHz).
Output points: 8 points (DC5V ~ DC24V) 6 points (differential).
Pulse output speed: the highest pulse/s 8M (2MHz).
High speed and stable input / output response
The high speed response can be achieved without the CPU module''s operation and bus performance,
Stable input and output response through hardware processing.
LD40PD01 is equipped with an external input and output interface and FPGA,
Therefore, high speed control can be realized without the influence of the scanning time of the CPU module and the bus performance (the input and output response time of the s instruction is realized).
Can achieve stable input and output response (processing time of the deviation of the ns level).
Through the intuitive tools for FPGA settings.
In the FPGA design process can be omitted in the past must be designed to deal with (HDL description, logic synthesis and time verification),
Reduce working hours. After receiving the product can be used immediately to verify the use of special tools, can significantly shorten the design time.
HF-SP51BK Operation manual/Instructions/Model selection sample download link: /searchDownload.html?Search=HF-SP51BK&select=5