PCI bus.
Support Japanese, English OS.
SI/QSI/H-PCF/ broadband H-PCF cable.
Dual loop controller network (control station / common station).
With external power supply function.
Province distribution network module in cabinet and device.
Link to connect the 64 stations when the fastest scanning time for 1 QS001CPU Application Manual QS001CPU User's Manual. 2ms (rate 2.5Mbps).
According to the transmission distance, the transmission rate is selected from 2 QS001CPU5Mbps, 625kbps and 156kbps.
CC-Link/LT from the station does not need any parameter settings.
Only need to set up the transmission speed in the master module, you can use the remote I/O.
MELSECNET/H network module capable of composing large scale flexible network system.
The MELSECNET/H network system includes the PLC network of the control station and the communication between the stations and the remote I/O network in the remote station remote I/O station QS001CPU Application Manual QS001CPU User's Manual.
Optical fiber loop system...... High speed communication of 10Mbps/25Mbps is realized.
The distance between stations, the length of the total cable length, strong anti-interference.
Coaxial bus system...... Using low cost coaxial cable, the network construction cost is lower than that of the optical fiber loop network QS001CPU Application Manual QS001CPU User's Manual.
Twisted pair bus system...... Combined with high performance price ratio network module and twisted pair cable,
The construction cost of network system is very low.Input and output points: 512 points.
Input / output data points: 8192 points.
Program capacity: 28k.
Basic command processing speed (LD command) S:0.2.
PLC in the program execution stage: according to the order of the user program order to store the order of each instruction,
After the corresponding operation and processing, the result is written to the output status regiister,
The contents of the output status register are changed with the execution of the program QS001CPU Application Manual QS001CPU User's Manual.
Output refresh phase: when all instructions are executed,
The output status register is sent to the ooutput latch in the output refresh stage,
And through a certain way (relay, transistor or transistor) output, drive the corresponding output equipment QS001CPU Application Manual QS001CPU User's Manual.